This invention relates to computer memories, and in particular to hardware and techniques for detection and repair of defects in computer memory arrays.
Computer memory arrays on chips involve a very large number of individual cells. For dynamic random access memories, the number of cells is very large. As a result, even low defect rates arising out of the manufacturing process result in an unacceptably low yield. Test procedures are applied to DRAM chips, usually on wafer-by-wafer basis. Every chip on each wafer is tested on specialized equipment, which identifies the locations of defective cells. Location information is then supplied to a controller for a laser repair device, which achieves a hardware fix. The repaired wafer is then tested again.
Such test and repair procedures result in higher yields. However, the procedures are expensive because of the need to employ specialized test and repair equipment.
In SRAM chips, and other chips with embedded logic, repairs are not ordinarily carried out. The size of arrays in SRAM chips and other such chips has been small enough that, even without repairs, acceptable yield has been obtained. Also, because SRAM chips are generally more specialized and manufactured in smaller quantities, the cost of configuring laser repair machines must be averaged over a relatively small number of wafers, when compared to DRAM chips.
In chips with embedded memories, it has become possible to have test procedures carried out by logic on the chip, known as built-in self-test units. The built-in self-test units for SRAM chips carry out a verification process resulting in a simple indication of whether there is a defect in the memory array. As defective chips are simply discarded, no additional information is required.
However, array size in SRAM chips is steadily increasing. Accuracy in manufacturing techniques is not increasing sufficiently rapidly to maintain yields. Furthermore, additional components, which were formerly in separate devices, are also being added to SRAM chips. The added components increase functionality of the chips, and are sometimes referred to as a system on a chip. These devices mean that individual chips are much more expensive, making discarding faulty chips undesirable.
According to one aspect of the invention, a reconfiguration memory device is provided associated with a main memory array. The reconfiguration memory device includes a table listing faulty addresses in the main memory array, and, associated with each faulty address, an address in a spare memory array. The reconfiguration memory device is coupled to an address line, so that when address information is received for the main memory array, the address information is also received by the reconfiguration memory device. The reconfiguration memory device is adapted to check the table to determine whether the received address information corresponds to a stored faulty address. The reconfiguration memory device is adapted to send an output signal that results in the address in the spare memory address array being addressed, if the received address information corresponds to a stored faulty address. This permits real time repair of the main memory.
According to another aspect of the invention, main memory addresses received on an address line are compared to faulty addresses stored in a look-up table in a device on the same substrate as the main memory. When a received address is found in the table of faulty addresses, a corresponding spare address is identified. The spare address identifies a location in a spare memory, also located on the substrate. The corresponding spare address is then addressed.
According to another aspect of the invention, a method is provided for correcting for faults in a computer main memory located on a substrate. One or more faulty addresses are identified in the main memory. The faulty addresses are stored in a reconfiguration device in the substrate. For each faulty address, a unique corresponding spare address is selected. The spare address identifies a location in a spare memory array also located on the substrate. The spare address is stored in the reconfiguration device associated with the corresponding main memory address. When a signal is received identifying one of the faulty address locations, the spare address location corresponding to that faulty address location is addressed.